By Sanjay Dabral, Timothy J. Maloney
The 1st accomplished advisor to ESD security and I/O designBasic ESD and I/O layout is the 1st booklet dedicated to ESD (electrostatic discharge) safety and input/output layout. Addressing the starting to be call for in for high-speed I/O designs, it bridges the space among ESD examine and present VLSI layout practices and gives a much-needed reference for working towards engineers who're often referred to as upon to benefit the topic at the job.This quantity offers an built-in therapy of ESD, I/O, and method parameter interactions that either I/O designers and method designers can use. It examines key components in I/O and ESD layout and checking out, and is helping the reader contemplate ESD and reliability concerns up entrance whilst making I/O offerings. Emphasizing readability and straightforwardness, this ebook makes a speciality of layout ideas that may be utilized generally as this dynamic box keeps to conform. simple ESD and I/O layout: * Describes thoughts for design-oriented ESD safety * Explains format tools that improve ESD safeguard designs * Addresses easy I/O designs, together with new difficulties resembling combined voltage interfaces * Discusses fabrication facets affecting ESD and I/O security * Illustrates thoughts utilizing quite a few figures and examples * Expresses machine physics by way of easy electric circuit versions * Cross-references the cloth to plain texts within the fieldEssential for engineers in and a person designing circuits, platforms, or units for destiny applied sciences, uncomplicated ESD and I/O layout is additionally an invaluable reference for researchers and graduate scholars desirous about middle VLSI layout or computing device structure.
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2-5. When the sum approaches 1, the current increases dramatically: (2-1) (2-2) (2-3) (2-4) (2-5) where a:l and a:2 are the current gain ofPNP and NPN transistors, respectively; and lc2 are the collector currents and leol and leo2 the reverse-biased col· lector currents of the NPN and PNP transistors, respectively. It is seen that as the sum ofa:j and a:2 tends to 1, I increases drastically. This is the case when the SCR latches up. This explains the latchup condition, but how does the SCR get initiated into latchup?
However, with the introduction of the silicided technology, this action has been large eliminated. This has led to nonunifonn current distribution to the device. Only a few fingers may take all the ESD current while other fingers do not share the stress, which leads to early failure. The perfonnance of the GGNMOS has correspondingly suffered. 3. Silicon-Controlled Rectifier (SCR) The SCR occurs inherently in CMOS technology because of the complementary nature of the devices, which require a well for isolation.
A recently implemented version of a current path scheme may look as in Figure 2-27. Here the diodes provide the links from pad to power supply and an NMOS core clamp between Vee and Vss ' Using such a simple scheme, successful ESD protection has been reported [Merrill, 1993]. It is noteworthy that most authors reported success when the current path model was used. New work is being published on using densely·packed PMOS devices for power supply clamping, including stacked devices for high-voltage power supply clamping [Maloney, 1998].